Frequency synthesis is a basic function provided on nearly every modem integrated circuit (IC). Multiple clock signals, each having a different frequency, must be generated simultaneously from a single fixed-frequency reference oscillator to meet the clocking needs of various digital and mixed-signal circuits in the IC. Frequency synthesis can be accomplished using various techniques, but the most common is to use a phase locked loop (PLL) or similar circuit. A PLL is feedback system that compares the output of a controllable oscillator to the output of a reference oscillator and uses the result of the comparison to adjust the controllable oscillator frequency upwards or downloads until the frequency difference between the controllable oscillator frequency and reference oscillator frequency is zero. The PLL can be made to output a frequency that is a multiple, N, of the controllable oscillator frequency by dividing the controllable oscillator frequency by N before the comparison with the reference oscillator frequency. For example, a stable 52 MHz clock can be synthesized from a 26 MHz reference oscillator frequency by dividing the output of the controllable oscillator by two.
If the clock signal frequencies to be synthesized are integer multiples of each other, i.e. harmonics, they can readily be generated by a single PLL in combination with one or more frequency multipliers and dividers. However, to generate clock signal frequencies that are non-harmonic or “fractional” multiples of each other, a more complex scheme is necessary. A straightforward solution is to provide a separate PLL for generating each clock signal. However, this approach is IC die area-intensive and power-intensive. Another known approach is to use a single PLL in combination with a fractional frequency divider.
Various methods of fractional frequency division are known. As illustrated in FIG. 1, a phase-switching fractional frequency divider 10 can be used in a PLL that generates clock signal frequencies that are fractional multiples of each other. For purposes of clarity, only the fractional frequency divider 10 of the PLL and not the PLL in its entirety is shown. In this example, the fractional modulus, i.e., the ratio between two non-harmonic frequencies to be synthesized, is 16.25. That is, fractional frequency divider 10 enables the PLL to generate a first clock signal having a frequency f and a second clock signal having a frequency f/16.25. Conventional phase-generator circuitry (not shown for purposes of clarity) generates a 0-degree phase signal 12 (f0°), a 90-degree phase signal 14 f90°), a 180-degree phase signal 16 (f180°), and a 270-degree phase signal 18 (f270°). That is, signals 12, 14, 16 and 18 have the same frequency f but are phase-separated in increments of 90°. All phase signals 12-18 are applied to a phase multiplexer 20, which produces a multiplexer output signal 22 (pout) in response to a multiplexer control signal 24 (psw). An integer frequency divider 26 divides the frequency of multiplexer output signal 22 by N, an integer (in this example, N=16), to produce an output signal 28 (fout). Integer frequency divider 26 commonly comprises a counter circuit. Output signal 28 is fed back into an AND gate 30, which performs a logical-AND of output signal 28 and a mode control signal 32 (int). The result of the logical-AND operation is applied to a phase controller 34, which in turn generates multiplexer control signal 24. When mode control signal 32 is high or logic-“1”, phase-switching fractional frequency divider 10 operates in fractional mode, where f out=f/(N+¼). When mode control signal 32 is low or logic-“0”, phase-switching fractional frequency divider 10 operates in an integer mode, where f out=f/N.
Ideally, i.e., in the absence of undesirable effects such as those caused by signal jitter and IC process variation, phase-switching fractional frequency divider 10 operates as shown in the timing diagram in FIG. 2. For purposes of clarity, only 0-degree phase signal 12 and 90-degree phase signal 14 are shown, but 180-degree phase signal 16 and 270-degree phase signal 18 are used in the same manner. In this example, in which N=16, integer frequency divider 26 is accordingly implemented as a 4-bit counter, in order to realize a fractional modulus of 16¼. The most-significant bit of the counter serves as the output of integer frequency divider 26, providing output signal 28 (fout). (Note that the complement of output signal 28 (f out) is shown in FIG. 2 for purposes of clarity.)
The timing diagram of FIG. 2 begins at time t=0, with the 4-bit counter of integer frequency divider 26 (FIG. 1) in a “1111” state and phase controller 34 outputting a multiplexer control signal 24 (psw) having a value that causes phase multiplexer 20 to select zero-degree phase signal 12 (f0°). At t=0 the 0th edge 38 of 0-degree phase signal 12 (f0°) clocks integer frequency divider 26, which places the 4-bit counter of integer frequency divider 26 in a “0000” state and causes the complement of output signal 28 (f out) to transition to a high or logic-“1” state, as shown in FIG. 2. The complement of output signal 28 remains high until the 7th edge (not shown) of zero-degree phase signal 12 (f0°). Then, at a switching time tsw, sometime after the 15th edge 42 of zero-degree phase signal 12 (f0°), phase controller 34 increments multiplexer control signal 24 (psw) and, in response, phase multiplexer 20 selects 90-degree phase signal 14 (f90°), as indicated by the arrow 44 in FIG. 2. Because this transition occurs after the 15th edge 46 of 90-degree phase signal 14 (f90°), edge 46 does not clock integer frequency divider 26. The next edge that clocks integer frequency divider 26 is the 0th edge 48 of 90-degree phase signal 14 (f90°), which is delayed by ¼ of a cycle relative to zero-degree phase signal 12 (f0°). Accordingly, fout=1/(15/f+1.25/j)=f/16.25.
There are two potential problems associated with phase-switching fractional frequency divider 10. First, the timing of phase multiplexer 20 transitioning or switching from one phase to the next, at time tsw, is critical. Although in the example or instance shown in FIG. 2 tsw occurs after the 15th edge 46 of 90-degree phase signal 14 (f90°), undesirable effects caused by signal jitter, IC process variation, etc., can cause tsw in other instances to occur earlier or later than shown. Providing circuitry to compensate for such indefiniteness is problematic, as there is no signal event at tsw from which phase controller 34 could be triggered to switch multiplexer control signal 24 (psw). If tsw is too early or too late relative to the 15th edge 46 of 90-degree phase signal 14 (f90°), glitching in multiplexer output signal 22 (pout) can occur, as illustrated in FIG. 3. As shown in this example, if the 15th edge 42 of zero-phase signal 12 (f0°) is used to trigger phase controller 34 to switch phase multiplexer 20 from zero-degree phase signal 12 (f0°), which is in a high or logic-“1” state at time tsw, to 90-degree phase signal (f90°), which is in a low or logic-“0” state at time tsw, then multiplexer output signal 22 (pout) could include an undefined transition or glitch 52. Although not shown, a similar glitch could also arise if the transition or switching time tsw were to occur after the falling edge of zero-degree phase signal 12 (f0°). In both cases, the glitch could cause integer frequency divider 26 to produce an error in the frequency division. Such glitches can be prevented by switching phase multiplexer 20 only when both the phase from which phase multiplexer 20 is to transition and the phase to which phase multiplexer 20 is to transition are both high or both low. These safety intervals 54 (Δt1) and 56 (Δt2) are shown in FIGS. 2 and 3.
Another potential issue with phase-switching fractional frequency divider 10 (FIG. 1) is an undesirably asymmetric duty cycle. Many circuits, such as switched capacitor networks, require a clock having a 50-percent duty cycle to operate properly. Because the high portion of output signal 28 (fout) is 8 periods of frequency f in duration and the low portion is 8.25 periods, the duty cycle is fundamentally asymmetric.
One attempt to solve the above-described glitching problem is to simply slow the transition between phases. A combination of slower slew rates and signal delay reduces the magnitude of the glitch. This approach is illustrated in FIG. 4. A dashed line 58 through multiplexer output signal 22 (pout) indicates the clock signal threshold level of integer frequency divider 26, which only clocks on positive edges. If the 15th edge 42 of zero-degree phase signal 12 (f0°) is used to trigger phase switching (as indicated by the arrow 60), a finite delay occurs before phase controller 34 increments multiplexer control signal 24 (psw) at tsw. At the time of such triggering, zero-degree phase signal 12 (f0°) has yet to reach its peak, and 90-degree phase signal 14 (f90°) is beginning to rise. The result is a gradual hand-off between phase signals, such that the rising edge of multiplexer output signal 22 (pout) exhibits a distortion 62 that is smaller and thus potentially less harmful than the glitch 52 described above with regard to FIG. 3. In the example or instance shown in FIG. 4, distortion 62 does not dip below the threshold indicated by dashed line 58 before rising again. Therefore, distortion 62 does not affect integer divider 26, which is properly clocked as the 15th edge of 90-degree phase signal 14 (f90°) continues to rise, as indicated by the other arrow 64. Of course, the magnitude of such a distortion depends on the delay of the signals and the slew rates, which can be affected by IC manufacturing process variation, supply voltage fluctuation, etc., and are thus difficult to control with precision.
Some have attempted to solve the above-described glitching problem by synchronizing the phase switching signal with the source signals. An example of such a circuit 10′ is shown in FIG. 5. In circuit 10′, a retimer 66 between phase controller 34 and phase multiplexer 20 generates a 0-degree phase switching signal 68, a 90-degree phase switching signal 70, a 180-degree phase switching signal 72, and a 270-degree phase switching signal 74. As shown in FIG. 6, although phase controller 34 responds to the 15th edge 76 of 0-degree phase signal 12 in the same manner as described above with regard to FIG. 1 (as indicated by the arrow 78), retimer 66 does not trigger 90-degree phase switching signal 70 until the 15th edge 80 of 90-degree phase signal (f90°). The 90-degree phase switching signal 70 causes phase multiplexer 20 to switch or transition from 0-degree phase signal 12 (f0°) to 90-degree phase signal 14 (f90°). Because 0-degree phase signal 12 is in the center of its peak when switching to 90-degree phase signal 14 occurs no glitch will occur (at least under ideal conditions; however, glitching is possible in instances in which noise, delay or other factors distort or skew the waveforms from the ideal squarewaves shown in this example). Although this scheme anchors tsw to a well-controlled signal edge, it does not address the above-described problem of an asymmetric duty cycle.